8SLVP1212I中文资料2:12,3.3V,2.5V LVPECL Fanout Buffer数据手册Renesas规格书

描述 Description

The 8SLVP1212I is a high-performance, 12 output differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1212I is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1212I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

特性 Features

Twelve low skew, low additive jitter LVPECL outputs
Two selectable, differential clock inputs
Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 15ps (typical)
Propagation delay: 550ps (maximum)
Low additive phase jitter, RMS: <50fs (typical)
Full 3.3V and 2.5V supply voltage
Device current consumption (IEE): 118mA (typical)
Available in Lead-free (RoHS 6), 40-Lead VFQFN package
-40°C to 85°C ambient operating temperature

应用 Application

• AI Industrial Robotics and Robotic Communication Solution