8SLVP1204I中文资料2:4,LVPECL Output Fanout Buffer数据手册Renesas规格书

描述 Description

The 8SLVP1204I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1204I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1204I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

特性 Features

• Four low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 5ps (typical)
• Propagation delay: 320ps (maximum)
• Low additive phase jitter, RMS
• fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 40fs (maximum)
• Maximum device current consumption (IEE): 60mA (maximum)
• Full 3.3V or 2.5V supply voltage
• Available in lead-free (RoHS 6), 16-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Supports case temperature ≤105°C operations