8SLVP1102I中文资料1:2,LVPECL Output Fanout Buffer数据手册Renesas规格书

描述 Description

The 8SLVP1102I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1102I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1102I ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and two low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device input. The device is optimized for low power consumption and low additive phase noise.

特性 Features

• Two low skew, low additive jitter LVPECL output pairs
• Differential PCLK, nPCLK pair can accept the following differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• Output skew: 5ps (typical)
• Propagation delay: 250ps (maximum)
• Low additive phase jitter, RMS
• fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 49fs (maximum)
• Full 3.3V or 2.5V supply voltage
• Maximum device current consumption (IEE): 34mA (maximum)
• Available in lead-free (RoHS 6), 16-Lead VFQFN package
• -40°C to 85°C ambient operating temperature