8SLVD1204-33I中文资料2:4, LVDS Output Fanout Buffer, 3.3 V数据手册Renesas规格书

描述 Description

The IDT8SLVD1204-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204-33I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

For a 2.5 V version of this device, please refer to the 8SLVD1204I.

特性 Features

• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 310ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 100fs (maximum)
• Full 3.3V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature

应用 Application

• AI Industrial Robotics and Robotic Communication Solution
• 手持式超声扫描仪