MSD Module Selectors

文件：246.15 Kbytes 页数：4 Pages

MALLORY

MSD Module Selectors

文件：246.15 Kbytes 页数：4 Pages

MALLORY

螺钉式接线端子

Keystone

包装：盒 类别：连接器，互连器件 线对板 描述：TERM BLK 3POS TOP ENTRY 5MM PCB

Keystone Electronics

Milli-Grid Connector System

Description: Milli-Grid Crimp Terminal, Chain, 0.38μm Select Gold, Lead free Application Signal, Wire-to-Board, Wire-to-Wire

文件：37.13 Kbytes 页数：2 Pages

Molex

莫仕

Milli-Grid Connector System

Description: Milli-Grid Crimp Terminal, Chain, 0.38μm Select Gold, Lead free Application Signal, Wire-to-Board, Wire-to-Wire

文件：37.13 Kbytes 页数：2 Pages

Molex

莫仕

LOW VOLTAGE, LVCMOS/ LVPECL-TO-LVPECL/ECL CLOCK GENERATOR

GENERAL DESCRIPTION The 873991 is a low voltage, low skew, 3.3V LVPECL or ECL Clock Generator . The 873991 has two selectable clock inputs. The PCLK, nPCLK pair can accept an LVPECL input and the TEST_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with

文件：532.67 Kbytes 页数：19 Pages

RENESAS

瑞萨

Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

GENERAL DESCRIPTION The 873991-147 is a low voltage, low skew, 3.3V LVPECL or ECL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 873991-147 has two selectable clock inputs. The CLK, nCLK pair can accept LVPECL, LVDS, LVHSTL, SSTL and HCSL input le

文件：530.24 Kbytes 页数：21 Pages

RENESAS

瑞萨

Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

GENERAL DESCRIPTION The 873995 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873995 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are

文件：518.049 Kbytes 页数：21 Pages

RENESAS

瑞萨

Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

GENERAL DESCRIPTION The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are

文件：540.24 Kbytes 页数：22 Pages

RENESAS

瑞萨