Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes 页数：17 Pages

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Low Skew,1-to-16 LVCMOS/LVTTL Clock Generator

The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2. • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)\n• Selectable differential CLK1, nCLK1 or LVCMOS clock input\n• CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n• CLK0 supports the following input types: LVCMOS, LVTTL\n• Maximum output freq;

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丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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瑞萨

Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input • CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Max

文件：898.68 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes 页数：17 Pages

IDT

丝印：ICS87016AYLF；Package：LQFP；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes 页数：17 Pages

IDT