丝印：ICS8701CYILF；Package：LQFP；Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

文件：341.61 Kbytes 页数：15 Pages

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瑞萨

丝印：ICS8701CYILF；Package：LQFP；Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

文件：341.61 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：ICS8701CYLF；Package：LQFP；Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • One LVCMOS/LVTTL clock input • Maximum output frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 250ps (maximum) • Part-to-part skew: 600ps (maximum) • Bank s

文件：373.8 Kbytes 页数：14 Pages

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瑞萨

丝印：ICS8701CYLF；Package：LQFP；Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • One LVCMOS/LVTTL clock input • Maximum output frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 250ps (maximum) • Part-to-part skew: 600ps (maximum) • Bank s

文件：373.8 Kbytes 页数：14 Pages

RENESAS

瑞萨

Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

文件：341.61 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：87021AIL；Package：SOIC；÷1/÷2 Differential-to-LVCMOS/LVTTL Clock Generator

FEATURES • Two single-ended LVCMOS/LVTTL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Additive phase jitter, RMS: 0.18ps (typical) • Output skew: 50p

文件：782.21 Kbytes 页数：14 Pages

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丝印：87021AIL；Package：SOIC；÷1/÷2 Differential-to-LVCMOS/LVTTL Clock Generator

FEATURES • Two single-ended LVCMOS/LVTTL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Additive phase jitter, RMS: 0.18ps (typical) • Output skew: 50p

文件：782.21 Kbytes 页数：14 Pages

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瑞萨

÷1/÷2 Differential-to-LVCMOS/LVTTL Clock Generator

FEATURES • Two single-ended LVCMOS/LVTTL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Additive phase jitter, RMS: 0.18ps (typical) • Output skew: 50p

文件：782.21 Kbytes 页数：14 Pages

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瑞萨

WCAP-PT5H Aluminum Polymer Capacitors

E General information: Aluminium Polymer Capacitors Storage Conditions:35°C,

文件：483.3 Kbytes 页数：7 Pages

WURTHWurth Elektronik GmbH & Co. KG, Germany.

伍尔特伍尔特集团

NEMA Contactor, Type S, reversing, horizontal, Size 00, 9A, 1 HP at 230 VAC, single phase, 3 pole, 120 VAC coil, open style

Main Product Type Contactor Product Range Type S Contactor Type Reversing

文件：132.74 Kbytes 页数：2 Pages

SCHNEIDER

施耐德