AXL E EC DI8 DO4 2A M12 6P

文件：333.82 Kbytes 页数：25 Pages

PHOENIXPHOENIX CONTACT

菲尼克斯德国菲尼克斯电气集团

INDUCTORS Inductors Designed for Nationals 150 KHz SIMPLE SWITCHERTM

文件：100.28 Kbytes 页数：1 Pages

FILTRAN

费尔兰特

Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer

The 8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the 8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100?. The 8543 has two selectable clock inputs • Four differential LVDS output pairs\n• Selectable differential CLK, nCLK or LVPECL clock inputs\n• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n• PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL\n• Maximu;

Renesas

瑞萨

包装：散装 类别：五金件，紧固件，配件 旋钮 描述：KNOB KNURLED 0.250\

Keystone Electronics

丝印：ICS8543AG09L；Package：TSSOP；Low Skew, 1-to-4, Differential-to- LVDS Fanout Buffer

Features • Four differential LVDS output pairs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum outpu

文件：1.34569 Mbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8543AG09L；Package：TSSOP；Low Skew, 1-to-4, Differential-to- LVDS Fanout Buffer

Features • Four differential LVDS output pairs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum outpu

文件：1.34569 Mbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8543BGILF；Package：TSSOP；Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

Features • Four differential LVDS output pairs • Selectable differential CLK/nCLK or LVPECL clock inputs • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK/nPCLK pair can accept the following differential input levels: LVPECL, CML, SST

文件：820.13 Kbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8543BGILF；Package：TSSOP；Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

Features • Four differential LVDS output pairs • Selectable differential CLK/nCLK or LVPECL clock inputs • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK/nPCLK pair can accept the following differential input levels: LVPECL, CML, SST

文件：820.13 Kbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8543AG09L；Package：TSSOP；Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

文件：996.29 Kbytes 页数：17 Pages

IDT

丝印：ICS8543AG09L；Package：TSSOP；Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

文件：996.29 Kbytes 页数：17 Pages

IDT