T-1 Subminiature Lamps

T-1¼ Subminiature Lamps

文件：33.49 Kbytes 页数：1 Pages

GILWAY

INDUCTORS Inductors Designed for Nationals 150 KHz SIMPLE SWITCHERTM

文件：100.28 Kbytes 页数：1 Pages

FILTRAN

费尔兰特

AXL E EC DI16 M12 6P

文件：323.29 Kbytes 页数：23 Pages

PHOENIXPHOENIX CONTACT

菲尼克斯德国菲尼克斯电气集团

丝印：8541；Package：VSSOP；SN74AC8541 Octal Buffers or Drivers With 3-State Outputs

1 Features • Wide operating range of 1.5V to 6V • Inputs accept voltages up to 6V • Continuous ±24mA output drive at 5V • Supports up to ±75mA output drive at 5V in short bursts • Drives 50Ω transmission lines • Maximum tpd of 6ns at 5V, 50pF load 2 Applications • Enable or disable a di

文件：1.71108 Mbytes 页数：28 Pages

TI

德州仪器

丝印：8541；Package：SOT23-5；OPERATION INSTRUCTION

文件：2.44234 Mbytes 页数：21 Pages

COREBAI

芯佰微

包装：散装 类别：五金件，紧固件，配件 旋钮 描述：KNOB KNURLED 0.125\

Keystone Electronics

M10X0.75 FEMALE THREAD DUST CAP W/ CHAIN

FEATURES M8 connector pin configurations: 3 pin, 4 pin, 5 pin, 6 pin Non-removable Contacts Meets IP67/IP68 water proof requirements -40°C to +85°C Temperature Range Available as loose piece or as pre-made M8 cables MATERIALS SHELL: Brass-Nickel Plated or Stainless Steel INSULATOR: PBT-B

文件：55.69 Kbytes 页数：1 Pages

NORCOMP

Low Skew, 1-to-4, LVCMOS/LVTTL-to-LVDS Fanout Buffer

General Description The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 85410

文件：407.49 Kbytes 页数：14 Pages

RENESAS

瑞萨

Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS Fanout Buffer

General Description The 854105I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105I provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 854

文件：474.56 Kbytes 页数：14 Pages

RENESAS

瑞萨

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

文件：386.95 Kbytes 页数：16 Pages

RENESAS

瑞萨