General Description

The 854105 is a low skew, high performance 1-to-4

LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage

Differential Signaling (LVDS), the 854105 provides a low power, low

noise solution for distributing clock signals over controlled

impedances of 100. The 854105 accepts an LVCMOS/LVTTL input

level and translates it to LVDS output levels.

Guaranteed output and part-to-part skew characteristics make the

854105 ideal for those applications demanding well defined

performance and repeatability.

Features

• Four differential LVDS output pairs

• One single-ended LVCMOS/LVTTL input

• CLK can accept the following input levels: LVCMOS, LVTTL

• Maximum output frequency: 250MHz

• Translates single-ended input signals to LVDS levels

• Additive phase jitter, RMS: 0.16ps (typical)

• Output skew: 55ps (maximum)

• Part-to-part skew: 350ps (maximum)

• Propagation delay: 1.62ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package

854105属于集成电路（IC） > 时钟缓冲器，驱动器。瑞萨科技有限公司制造生产的854105时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。