Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS Fanout Buffer

General Description The 854105I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105I provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 854

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Low Skew,1-to-4,LVCMOS/LVTTL-to-LVDS Fanout Buffer

The 854105I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105I provides a low power, low noise solution for distributing clock signals over controlled impedances of 100?. The 854105I accepts an LVCMOS/LVTT ·Four differential LVDS output pairs\n·One single-ended LVCMOS/LVTTL input\n·CLK can accept the following input levels: LVCMOS, LVTTL\n·Maximum output frequency: 250MHz\n·Translates single-ended input signals to LVDS levels\n·Additive phase jitter, RMS: 0.16ps (typical)\n·Output skew: 72ps (maximum);

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瑞萨

Low Skew, 1-to-4, LVCMOS/LVTTL-to-LVDS Fanout Buffer

General Description The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 85410

文件：407.49 Kbytes 页数：14 Pages

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瑞萨

原装

QORVO

威讯联合

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SOT-23

UTC/友顺

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