丝印：ICS85408BGLF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

文件：539.82 Kbytes 页数：17 Pages

RENESAS

瑞萨

丝印：ICS85408BGLF；Package：TSSOP；Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes 页数：16 Pages

IDT

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:8 700MHZ 24TSSOP

RENESAS

瑞萨

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

文件：466.01 Kbytes 页数：12 Pages

ICST

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

文件：466.01 Kbytes 页数：12 Pages

ICST

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

文件：466.01 Kbytes 页数：12 Pages

ICST