丝印：85222AML；Package：SOIC；Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

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瑞萨

丝印：85222AML；Package：SOIC；Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：85222AML；Package：SOIC；Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：85222AML；Package：SOIC；Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

RENESAS

瑞萨

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes 页数：13 Pages

IDT

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes 页数：13 Pages

IDT