丝印：85222AML；Package：SOIC；Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

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Dual LVCMOS / LVTTL-to-Differential HSTL Translator

文件：184.46 Kbytes 页数：14 Pages

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1-to-2, LVCMOS/LVTTL-to-Differential HSTL Translator

文件：211.53 Kbytes 页数：12 Pages

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Dual LVCMOS / LVTTL-to-Differential HSTL Translator

文件：184.46 Kbytes 页数：14 Pages

IDT

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

文件：184.46 Kbytes 页数：14 Pages

IDT

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes 页数：13 Pages

IDT

Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes 页数：13 Pages

IDT

Low-Skew, 1-to-2 LVCMOS/LVTTL-to-HSTL Fanout Buffer

The 85222-02 is a 1-to-2 LVCMOS / LVTTL-to- Differential HSTL translator. The 85222-02 has one single ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications ·1-to-2 LVCMOS/LVTTL to HSTL fanout buffer\n·Output voltage high: 1.4V (maximum)\n·Translates single-ended input signals to HSTL output levels\n·Output frequency range: 0 - 350MHz\n·Part to part skew: 250ps (maximum)\n·Output skew: 25 ps (maximum)\n·Voltage supply: 3.3V\n·0°C to 70°C ambient operati;

Renesas

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连接器附件

TE

泰科

包装：盒 描述：E-J MK-II(+) 15P CAP DBL

TE Connectivity AMP Connectors