Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

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Dual LVCMOS / LVTTL-TO-Differential

文件：152.67 Kbytes 页数：13 Pages

IDT

Dual LVCMOS / LVTTL-TO-Differential

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包装：散装 类别：工具 扳手 描述：WR RAT REV S 10MMX12MM

ATG

Dual LVCMOS / LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full

文件：390.59 Kbytes 页数：15 Pages

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1-to-2, LVCMOS/LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • One LVCMOS/LVTTL clock input • CLK input can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 250ps (maximum) • Propagation delay: 1.25ns (maximum) • V OH : 1.4V (maximum) • Output crossov

文件：364.88 Kbytes 页数：13 Pages

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1-TO-2 LVCMOS / LVTTL-TO DIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-02 has one single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels

文件：130.639 Kbytes 页数：10 Pages

ICST

丝印：5222A01L；Package：SOIC；Dual LVCMOS / LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full

文件：390.59 Kbytes 页数：15 Pages

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丝印：5222A01L；Package：SOIC；Dual LVCMOS / LVTTL-to-Differential HSTL Translator

FEATURES • Two differential HSTL outputs • CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 375ps (maximum) • Propagation delay: 1075ps (maximum) • VOH: 1.4V (maximum) • Full

文件：390.59 Kbytes 页数：15 Pages

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丝印：85222AML；Package：SOIC；Dual LVCMOS / LVTTL-TO-Differential LVHSTL Translator

FEATURES • 2 differential LVHSTL outputs • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) •

文件：358.01 Kbytes 页数：14 Pages

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