500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequeny Synthesizer

FEATURES • Dual differential 3.3V or 2.5V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 20.83MHz to 500MHz • Crystal input frequency range: 14MHz to 27MHz • VCO range: 250MHz to 500MHz • Parallel or serial interface for programmi

文件：501.43 Kbytes 页数：22 Pages

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丝印：ICS30S07AIL；Package：VFQFN；Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

文件：1.09248 Mbytes 页数：27 Pages

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丝印：ICS30S07AIL；Package：VFQFN；Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

文件：1.09248 Mbytes 页数：27 Pages

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丝印：ICS430S10AIL；Package：TQFP；Clock Generator for Cavium Processors

Features • One selectable clock for DDR 400/533/667, LVPECL/LVDS interface levels • Nine LVCMOS/ LVTTL outputs, 15Ω typical output impedance • Selectable external crystal or differential input source • Crystal oscillator interface designed for 25MHz, parallel resonant crystal • Differential

文件：1.79228 Mbytes 页数：30 Pages

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丝印：ICS430S10AIL；Package：TQFP；Clock Generator for Cavium Processors

Features • One selectable clock for DDR 400/533/667, LVPECL/LVDS interface levels • Nine LVCMOS/ LVTTL outputs, 15Ω typical output impedance • Selectable external crystal or differential input source • Crystal oscillator interface designed for 25MHz, parallel resonant crystal • Differential

文件：1.79228 Mbytes 页数：30 Pages

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丝印：ICS0S10BI02L；Package：TQFP；Clock Generator for Cavium Processors

Features • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels • Nine LVCMOS/ LVTTL outputs, 20 typical output impedance • Selectable external crystal or differential (single-ended) input source • Crystal oscillator interface designed for 25MHz, parall

文件：840.11 Kbytes 页数：32 Pages

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丝印：ICS0S10BI02L；Package：TQFP；Clock Generator for Cavium Processors

Features • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels • Nine LVCMOS/ LVTTL outputs, 20 typical output impedance • Selectable external crystal or differential (single-ended) input source • Crystal oscillator interface designed for 25MHz, parall

文件：840.11 Kbytes 页数：32 Pages

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Clock Generator for Cavium Processors

Features • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels • Nine LVCMOS/ LVTTL outputs, 20 typical output impedance • Selectable external crystal or differential (single-ended) input source • Crystal oscillator interface designed for 25MHz, parall

文件：840.11 Kbytes 页数：32 Pages

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Clock Generator for Cavium Processors

General Description The 8430S10I-03 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both th

文件：830.35 Kbytes 页数：32 Pages

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High-Performance Fractional-N Frequency Synthesizer

文件：843.66 Kbytes 页数：27 Pages

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