T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

文件：456.81 Kbytes 页数：32 Pages

IDT

T1/E1/OC3 WAN PLL With Dual Reference Inputs

The 82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3012 provides 9 types • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces\n• Supports ITU-T G.813 Option 1 clocks\n• Supports ITU-T G.812 Type IV clocks\n• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface\n• Selectable referen;

Renesas

瑞萨

T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks • Supports ITU-T G.812 Type IV clocks • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Sele

文件：633.57 Kbytes 页数：33 Pages

RENESAS

瑞萨

T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks • Supports ITU-T G.812 Type IV clocks • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Sele

文件：633.57 Kbytes 页数：33 Pages

RENESAS

瑞萨

Package：56-BSSOP（0.295"，7.50mm 宽）；包装：管件 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL WAN T1/E1/OC3 DUAL 56SSOP

Renesas Electronics America Inc

Package：56-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL WAN T1/E1/OC3 DUAL 56SSOP

Renesas Electronics America Inc