Hex inverting Schmitt trigger

The 74VHC14; 74VHCT14 are a high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74VHC14; 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming • Balanced propagation delays\n• All inputs have Schmitt-trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• The 74VHC14 operates with CMOS input level\n• The 74VHCT14 operates with TTL input level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115;

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Hex inverting Schmitt trigger

General description The 74VHC14; 74VHCT14 are a high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74VHC14; 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They are capab

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NEXPERIA

安世

Package：14-VFQFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 门和反相器 描述：IC INVERTER 6CH 1-INP 14DHVQFN

Nexperia USA Inc.

Hex inverting Schmitt trigger

General description The 74VHC14; 74VHCT14 are a high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74VHC14; 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They are capab

文件：623.43 Kbytes 页数：16 Pages

NEXPERIA

安世

Hex inverting Schmitt trigger

General description The 74VHC14; 74VHCT14 are a high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74VHC14; 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They are capab

文件：623.43 Kbytes 页数：16 Pages

NEXPERIA

安世

Hex Schmitt Inverter

The MC74VHCT14A is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Features • High Speed: tPD = 5.5 ns (Typ) at VCC = 5.0 V • Lo

文件：147.29 Kbytes 页数：8 Pages

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