74LVC2G74GF - Single D-type flip-flop with set and reset; positive edge trigger

Single D-type flip-flop with set and reset; positive edge trigger - The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial pow ·Wide supply voltage range from 1.65 V to 5.5 V\n·5 V tolerant inputs for interfacing with 5 V logic\n·High noise immunity\n·Complies with JEDEC standard: ·JESD8-7 (1.65 V to 1.95 V)\n·JESD8-5 (2.3 V to 2.7 V)\n·JESD8-B/JESD36 (2.7 V to 3.6 V);

Nexperia

安世

Single D-type flip-flop with set and reset; positive edge trigger

文件：123.84 Kbytes 页数：21 Pages

恩XP

Package：8-XFDFN；包装：卷带（TR）剪切带（CT） 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 1BIT 8XSON

Nexperia USA Inc.

Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 页数：18 Pages

NEXPERIA

安世