Dual buffer gate

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恩XP

Dual buffer gate

文件：146.5 Kbytes 页数：17 Pages

恩XP

Dual buffer gate

The 74LVC2G34 provides two buffers.\n Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outp • Wide supply voltage range from 1.65 V to 5.5 V\n• 5 V tolerant inputs for interfacing with 5 V logic\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000;

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Package：6-XFDFN；包装：散装 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUFFER NON-INVERT 5.5V 6XSON

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