Dual inverter

The 74LVC2G04 provides the dual inverting buffer.\n Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry dis • Wide supply voltage range from 1.65 V to 5.5 V\n• 5 V tolerant inputs for interfacing with 5 V logic\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000;

Nexperia

安世

Dual inverter

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恩XP

Package：6-XFDFN；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 描述：IC INVERTER 2CH 2-INP 6XSON

Nexperia USA Inc.

Dual inverter

文件：85.59 Kbytes 页数：14 Pages

PANASONIC

松下

Dual inverter

1. General description The 74LVC2G04 is a dual inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise a

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NEXPERIA

安世