2-input EXCLUSIVE-OR gate

DESCRIPTION The 74LVC1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

文件：69.46 Kbytes 页数：12 Pages

PHI

PHI

2-input EXCLUSIVE-OR gate

DESCRIPTION The 74LVC1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

文件：86.02 Kbytes 页数：15 Pages

PHI

PHI

2-input EXCLUSIVE-OR gate

description The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. T

文件：87.59 Kbytes 页数：14 Pages

恩XP

丝印：VH；Package：SOT353-1；2-input EXCLUSIVE-OR gate

1. General description The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using I

文件：255.83 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：VH；Package：TSSOP5；2-input EXCLUSIVE-OR gate

1. General description The 74LVC1G86-Q100 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications us

文件：220.76 Kbytes 页数：11 Pages

NEXPERIA

安世

丝印：VH；Package：TSSOP5；2-input EXCLUSIVE-OR gate

文件：183.61 Kbytes 页数：13 Pages

NEXPERIA

安世

2-input EXCLUSIVE-OR gate

The 74LVC1G86‑Q100 provides the 2‑input EXCLUSIVE‑OR function.\n Inputs can be driven from either 3.3V or 5V devices. These features allow the use of these devices in a mixed 3.3V and 5V environment.\n This device is fully specified for partial Power-down applications using IOFF. The IOFF circ • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Wide supply voltage range from 1.65 V to 5.5 V\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD;

Nexperia

安世

Package：5-TSSOP，SC-70-5，SOT-353；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 1CH 2-INP 5TSSOP

Nexperia USA Inc.

Package：5-TSSOP，SC-70-5，SOT-353；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 1CH 2-INP 5TSSOP

Nexperia USA Inc.

Package：5-TSSOP，SC-70-5，SOT-353；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 1CH 2-INP 5TSSOP

Nexperia USA Inc.