Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. FEATURES

文件：97.02 Kbytes 页数：18 Pages

PHI

PHI

Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Features ■ Wide supply voltage range from 1.65 V to 5.5 V ■ Hig

文件：89.9 Kbytes 页数：16 Pages

恩XP

丝印：V79；Package：SC-74A；Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Features and benefits ■ Automotive product qualification in

文件：794.73 Kbytes 页数：15 Pages

NEXPERIA

安世

丝印：VP；Package：SOT353-1；Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V

文件：275.95 Kbytes 页数：19 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Features ■ Wide supply voltage range from 1.65 V to 5.5 V ■ Hig

文件：89.9 Kbytes 页数：16 Pages

恩XP

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. FEATURES

文件：97.02 Kbytes 页数：18 Pages

PHI

PHI

丝印：VP；Package：TSSOP5；Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Features and benefits ■ Automotive product qualification in

文件：794.73 Kbytes 页数：15 Pages

NEXPERIA

安世

丝印：VP；Package：SOT1226-3；Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V

文件：275.95 Kbytes 页数：19 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Features and benefits ■ Automotive product qualification in

文件：794.73 Kbytes 页数：15 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.\n Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation • Wide supply voltage range from 1.65 V to 5.5 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• ±24 mA output drive (VCC = 3.0 V)\n• Latch-up performance exceeds 250 mA\n• Inputs accept voltages up;

Nexperia

安世