Single 2-input OR gate

DESCRIPTION The 74LVC1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95

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PANASONIC

松下

Single 2-input OR gate

General description The 74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower i

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恩XP

丝印：VG；Package：SOT886；Single 2-input OR gate

1. General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inp

文件：255.33 Kbytes 页数：16 Pages

NEXPERIA

安世

Single 2-input OR gate

General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input ri

文件：282.32 Kbytes 页数：17 Pages

NEXPERIA

安世

丝印：VG；Package：XSON6；Single 2-input OR gate

1. General description The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slowe

文件：242.86 Kbytes 页数：14 Pages

NEXPERIA

安世

丝印：VG；Package：XSON6；Single 2-input OR gate

1. General description The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slowe

文件：217.28 Kbytes 页数：12 Pages

NEXPERIA

安世

Single 2-input OR gate

The 74LVC1G32 provides one 2-input OR function.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and f • Wide supply voltage range from 1.65 V to 5.5 V\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8-B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• ±24 mA outp;

Nexperia

安世

Single 2-input OR gate

Panasonic

松下

Single 2-input OR gate

The 74LVC1G32-Q100 provides one 2-input OR function.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.65 V to 5.5 V\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• ;

Nexperia

安世

Package：6-XFDFN；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE OR 1CH 2-INP 6XSON

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