74LVC1G17GX

Single Schmitt trigger buffer

Generaldescription The74LVC1G17providesabufferfunctionwithSchmitttriggerinput.Itiscapableoftransformingslowlychanginginputsignalsintosharplydefinedoutputs. Theinputcanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallowstheuseofthisdeviceinamixed3.3V

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74LVC1G17GX

丝印：VJ；Package：SOT1226-3；Single Schmitt trigger buffer

1.Generaldescription The74LVC1G17isasinglebufferSchmitt-trigger.Inputscanbedrivenfromeither3.3Vor 5Vdevices.Thisfeatureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5V environments.Thisdeviceisfullyspecifiedforpartialpowerdownapplicationsusi

74LVC1G17GX

Single Schmitt trigger buffer; • Wide supply voltage range from 1.65 V to 5.5 V\n• High noise immunity\n• Complies with JEDEC standard• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V\n• MM: JESD22-A115-A exceeds 200 V\n\n• ±24 mA output drive (VCC = 3.0 V)\n• CMOS low power consumption\n• Latch-up performance exceeds 250 mA\n• Direct interface with TTL levels\n• Unlimited rise and fall times\n• Inputs accept voltages up to 5 V\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined outputs.\n The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n

74LVC1G17GX4

Single Schmitt trigger buffer; • Wide supply voltage range from 1.65 V to 5.5 V\n• High noise immunity\n• Complies with JEDEC standard• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM: ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V\n• MM: JESD22-A115-A exceeds 200 V\n\n• ±24 mA output drive (VCC = 3.0 V)\n• CMOS low power consumption\n• Latch-up performance exceeds 250 mA\n• Direct interface with TTL levels\n• Unlimited rise and fall times\n• Inputs accept voltages up to 5 V\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined outputs.\n The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n

74LVC1G17GX4

丝印：VJ；Package：SOT1269-2；Single Schmitt trigger buffer

1.Generaldescription The74LVC1G17isasinglebufferSchmitt-trigger.Inputscanbedrivenfromeither3.3Vor 5Vdevices.Thisfeatureallowstheuseofthesedevicesastranslatorsinmixed3.3Vand5V environments.Thisdeviceisfullyspecifiedforpartialpowerdownapplicationsusi

74LVC1G17GX,125

Package：4-XFDFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUFFER NON-INVERT 5.5V 5X2SON

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74LVC1G17GX4Z

Package：4-XFDFN；包装：卷带（TR） 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUFFER NON-INVERT 5.5V 4X2SON

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