Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

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PHI

飞利浦

Quad 2-input NAND gate Rev. 7 ??25 April 2012

文件：197.76 Kbytes 页数：14 Pages

PHI

飞利浦

Quad 2-input NAND gate

The 74LVC00A provides four 2-input NAND gates.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V appl • 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V)\n• JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n• E;

Nexperia

安世

Package：14-SSOP（0.209"，5.30mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE NAND 4CH 2-INP 14SSOP

Nexperia USA Inc.

Package：14-SSOP（0.209"，5.30mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE NAND 4CH 2-INP 14SSOP

Nexperia USA Inc.