Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

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Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

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Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

文件：125.21 Kbytes 页数：12 Pages

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Dual D-type flip-flop with set and reset; positive-edge trigger

文件：1.05556 Mbytes 页数：17 Pages

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Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Informatio • Wide operating voltage: 1.0 V to 5.5 V\n• Optimized for Low Voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40°C to +85°C and from -40°C to +125°C;

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D-Type Flip-Flops

Dual D-type flip-flop with set and reset; positive-edge trigger - The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inp ·Wide operating voltage: 1.0 V to 5.5 V\n·Optimized for Low Voltage applications: 1.0 V to 3.6 V\n·Direct interface with TTL levels (2.7 V to 3.6 V)\n·ESD protection:·HBM JESD22-A114F exceeds 2000 V\n·MM JESD22-A115-A exceeds 200 V;

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Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Infor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.0 V to 5.5 V\n• Optimized for low voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ES;

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Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14SO

Nexperia USA Inc.

Package：14-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14SSOP

Nexperia USA Inc.

Package：14-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14SSOP

Nexperia USA Inc.