74LV164D-Q100中文资料8-bit serial-in/parallel-out shift register数据手册Nexperia规格书

描述 Description

The 74LV164-Q100 is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164-Q100 and 74HCT164-Q100.
The 74LV164-Q100 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB). Either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP). It enters Q0, which is the logical AND-function of the two data inputs (DSA and DSB). Data inputs DSA and DSB, existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40°C to +85°C and from -40°C to +125°C

• Wide operating voltage: 1.0 V to 5.5V
• Optimized for low-voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical output ground bounce < 0.8 V at VCC = 3.3V and Tamb = 25°C
• Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb=25°C
• Gated serial data inputs
• Asynchronous master reset
• ESD protection:
• MIL-STD-833, method 3015 exceeds 2000V
• HBM JESD22-A114F exceeds 2000V
• MM JESD22-A115-A exceeds 200 V (C = 200pF, R = 0Ω)