Nine wide Schmitt trigger buffer/line driver; inverting

GENERAL DESCRIPTION The 74HC/HCT9014 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9014 are nine wide Schmitt trigger inverting buffer/line drivers with Schmitt trigger inpu

文件：43.76 Kbytes 页数：7 Pages

PHI

PHI

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

文件：46.1 Kbytes 页数：7 Pages

PHI

PHI

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

文件：46.1 Kbytes 页数：7 Pages

PHI

PHI

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

文件：46.1 Kbytes 页数：7 Pages

PHI

PHI

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

文件：46.1 Kbytes 页数：7 Pages

PHI

PHI

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

文件：46.1 Kbytes 页数：7 Pages

PHI

PHI

PLL with band gap controlled VCO

General description The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. Features ■ Operation power supply voltage range from 4.5 V to 5.5 V ■ Low power consumption ■ Inhibit control for ON/OFF keying and for low standby powe

文件：230.81 Kbytes 页数：43 Pages

恩XP

PLL with bandgap controlled VCO

GENERAL DESCRIPTION The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with “JEDEC standard no. 7A”. FEATURES • Low power consumption • Centre frequency up to 17 MHz (typ.) at VCC = 5.5 V • Choice of two phase comparators(1): – EXCLUSIVE-OR (PC

文件：240.35 Kbytes 页数：40 Pages

PHI

PHI

PLL with band gap controlled VCO

1. General description The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits

文件：667.87 Kbytes 页数：36 Pages

NEXPERIA

安世

PLL with band gap controlled VCO

1. General description The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits

文件：667.87 Kbytes 页数：36 Pages

NEXPERIA

安世