Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

文件：120.16 Kbytes 页数：22 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 页数：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 页数：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

文件：299.12 Kbytes 页数：19 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes 页数：21 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes 页数：22 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 页数：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

文件：120.16 Kbytes 页数：22 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 页数：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 页数：21 Pages

恩XP