Octal D-type transparent latch; 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

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PHI

飞利浦

Octal D-type transparent latch 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

文件：158.64 Kbytes 页数：21 Pages

PHI

飞利浦

Octal D-type transparent latch; 3-state

1. General description The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will

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安世安世半导体(中国)有限公司

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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TI

德州仪器

Octal D-type transparent latch; 3-state

General description The 74HC573-Q100; 74HCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Grad

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恩XP

Octal D-type transparent latch; 3-state

1. General description The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch ou

文件：274.77 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Octal D-type transparent latch; 3-state

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresp • Input levels:• For 74HC573: CMOS level\n• For 74HCT573: TTL level\n\n• Inputs and outputs on opposite sides of package allowing easy interface with microprocessors\n• Useful as input or output port for microprocessors and microcomputers\n• 3-state non-inverting outputs for bus-oriented application;

Nexperia

安世

Octal D-type transparent latch; 3-state

The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time i • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74HC573-Q100: CMOS level\n• For 74HCT573-Q100: TTL level\n\n• Inputs and outputs on opposite sides of package allowing easy interface with micr;

Nexperia

安世

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC OCTAL D TRANSP LATCH 20TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC OCTAL D TRANSP LATCH 20TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司