14-stage binary ripple counter

1. General description The 74HC4020-Q100; 74HCT4020-Q100 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR

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14-stage binary ripple counter

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14-stage binary ripple counter

The 74HC4020-Q100; 74HCT4020-Q100 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH‑to‑LOW transition of CP. A HIGH on MR clears all counter stages and • Automotive product qualification in accordance with AEC‑Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC4020-Q100: CMOS level\n• For 74HCT4020-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 ex;

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Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC RIPPLE COUNTER 14ST 16TSSOP

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