74HCT390PW

Dual decade ripple counter

GENERALDESCRIPTION The74HC/HCT390arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES •TwoBCDdecadeorbi-quinarycounters •Onepackagecanbeconfiguredtodivide-

PHI

74HCT390PW

Dual decade ripple counter

1.Generaldescription The74HC390;74HCT390isadual4-bitdecaderipplecounterdividedintofourseparatelyclocked sections.Thecountershavetwodivide-by-2sectionsandtwodivide-by-5sections.Thesesections shareanasynchronousmasterresetinput(nMR)andcanbeusedinaBCDdecad

74HCT390PW

Dual decade ripple counter; • Input levels:• For 74HC390: CMOS level\n• For 74HCT390: TTL level\n\n• Two BCD decade or bi-quinary counters\n• One device can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100\n• Two master reset inputs to clear each decade counter individually\n• Supply voltage range from 4.5 V to 5.5 V\n• High noise immunity\n• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n• Complies with JEDEC standard JESD7A (4.5 V to 5.5 V)\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decade or bi-quinary configuration. If master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clocks (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100. Each section is triggered by the HIGH-to-LOW transition of the clock inputs (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nQ3 output is connected to the nCP0 input and nQ0 becomes the decade output. A HIGH on the nMR input overrides the clocks and sets the four outputs LOW. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

CD74HCT390

High-SpeedCMOSLogicDualDecadeRippleCounter

CD74HCT390

High-SpeedCMOSLogicDualDecadeRippleCounter

CD74HCT390

HighSpeedCMOSLogicDualDecadeRippleCounter

CD74HCT390

High-SpeedCMOSLogicDualDecadeRippleCounter

CD74HCT390E

HighSpeedCMOSLogicDualDecadeRippleCounter

CD74HCT390E

High-SpeedCMOSLogicDualDecadeRippleCounter

CD74HCT390E

High-SpeedCMOSLogicDualDecadeRippleCounter