Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive,

文件：60.76 Kbytes 页数：8 Pages

PHI

飞利浦

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirement

文件：259.93 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive,

文件：60.76 Kbytes 页数：8 Pages

PHI

飞利浦

Octal D-type flip-flop; positive-edge trigger; 3-state

The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3‑state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip‑flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock ( • Input levels:• For 74HC374: CMOS level\n• For 74HCT374: TTL level\n\n• Octal bus interface\n• Non-inverting 3-state outputs\n• 8-bit positive, edge-triggered register\n• Common 3-state output enable input\n• Independent register and 3-state buffer operation\n• Complies with JEDEC standard no. 7 A\;

Nexperia

安世

Octal D-type flip-flop; positive-edge trigger; 3-state

The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3‑state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip‑flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock ( • Input levels:• For 74HC374: CMOS level\n• For 74HCT374: TTL level\n\n• Octal bus interface\n• Non-inverting 3-state outputs\n• 8-bit positive, edge-triggered register\n• Common 3-state output enable input\n• Independent register and 3-state buffer operation\n• Complies with JEDEC standard no. 7 A\;

Nexperia

安世

Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SO

Nexperia USA Inc.

Package：20-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

Nexperia USA Inc.

Package：20-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SSOP

Nexperia USA Inc.