8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

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PHI

飞利浦

8-bit addressable latch

General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A.

文件：134.88 Kbytes 页数：21 Pages

恩XP

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

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安世安世半导体(中国)有限公司

8-bit addressable latch

文件：174.08 Kbytes 页数：23 Pages

恩XP

8-bit addressable latch

General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A.

文件：134.88 Kbytes 页数：21 Pages

恩XP

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

文件：87.02 Kbytes 页数：11 Pages

PHI

飞利浦

8-bit addressable latch

General description The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

文件：261.35 Kbytes 页数：20 Pages

恩XP

8-bit addressable latch

1. General description The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-a

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NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

8-bit addressable latch

文件：174.08 Kbytes 页数：23 Pages

恩XP

8-bit addressable latch

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their pre • Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily expandable\n• Common reset input\n• Useful as a 3-to-8 active HIGH decoder\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74H;

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