74HCT166D

8-bit parallel-in/serial-out shift register

GENERALDESCRIPTION The74HC/HCT166arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT166are8-bitshiftregisterswhichhaveafullysynchronousserialorparalleldataentry

PHI

74HCT166D

8-bit parallel-in/serial out shift register

1.Generaldescription The74HC166;74HCT166isan8-bitserialorparallel-in/serial-outshiftregister.Thedevice featuresaserialdatainput(DS),eightparalleldatainputs(D0toD7)andaserialoutput(Q7). Whentheparallelenableinput(PE)isLOW,thedatafromD0toD7isloadedin

74HCT166D

8-bit parallel-in/serial-out shift register; • Synchronous parallel-to-serial applications\n• Synchronous serial input for easy expansion\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC166: CMOS level\n• For 74HCT166: TTL level\n\n• ESD protection:• HBM JESD22-A114E exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40°C to +85°C and from -40°C to +125°C\n;

The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW‑to‑HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW‑to‑HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW‑to‑HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HCT166DB

8-bit parallel-in/serial-out shift register

GENERALDESCRIPTION The74HC/HCT166arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT166are8-bitshiftregisterswhichhaveafullysynchronousserialorparalleldataentry

PHI

74HCT166DB

74HCT166DB - 8-bit parallel-in/serial-out shift register; ·Synchronous parallel-to-serial applications\n·Synchronous serial input for easy expansion\n·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC166: CMOS level\n·For 74HCT166: TTL level\n;

8-bit parallel-in/serial-out shift register - The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW‑to‑HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW‑to‑HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW‑to‑HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

74HCT166D-Q100

8-bit parallel-in/serial out shift register

1.Generaldescription The74HC166-Q100;74HCT166-Q100isan8-bitserialorparallel-in/serial-outshiftregister.The devicefeaturesaserialdatainput(DS),eightparalleldatainputs(D0toD7)andaserialoutput (Q7).Whentheparallelenableinput(PE)isLOW,thedatafromD0toD7is

74HCT166D-Q100

8-bit parallel-in/serial out shift register; • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 vC and from -40 °C to +125 °C\n\n• Synchronous parallel-to-serial applications\n• Synchronous serial input for easy expansion\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC166-Q100: CMOS level\n• For 74HCT166-Q100: TTL level\n\n• ESD protection:• MIL-STD-883, method 3015 exceeds 2000 V\n• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n• Multiple package options\n;

The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HCT166D-Q100

8-bit parallel-in/serial out shift register

74HCT166D,653

Package：16-SOIC（0.154"，3.90mm 宽）；包装：管件 功能：并行或串行至串行 类别：集成电路（IC） 移位寄存器 描述：IC SHIFT REG 8BIT PI-SO 16SOIC

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74HCT166DB,112

Package：16-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：并行或串行至串行 类别：集成电路（IC） 移位寄存器 描述：IC 8BIT SHIFT REGISTER 16-SSOP

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