3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

文件：50.49 Kbytes 页数：7 Pages

PHI

飞利浦

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Demultiplexing capability ■ Multiple input enable for easy expansion ■ Complies with JEDEC standard no. 7A ■ Ideal for memory chi

文件：211.62 Kbytes 页数：19 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

文件：274.63 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

文件：211.62 Kbytes 页数：19 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Demultiplexing capability ■ Multiple input enable for easy expansion ■ Complies with JEDEC standard no. 7A ■ Ideal for memory chi

文件：211.62 Kbytes 页数：19 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

文件：50.49 Kbytes 页数：7 Pages

PHI

飞利浦

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Grade 1) ◆ Specified from -40 °C to +85 °C and from -40 °

文件：241.85 Kbytes 页数：18 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This m

文件：273.19 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

文件：211.62 Kbytes 页数：19 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy par • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC138: CMOS level\n• For 74HCT138: TTL level\n\n• Demultiplexing capability\n• Multiple input enable for easy expansion\n• Ideal for memory chip select decoding\n• Active LOW mutually exclusive outputs\n• ESD protection:• HBM JESD22-A114F;

Nexperia

安世