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74HCT132

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

文件:70.63 Kbytes 页数:8 Pages

PHI

PHI

PHI

74HCT132

Quad 2-input NAND Schmitt trigger

1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals

文件:269.66 Kbytes 页数:16 Pages

NEXPERIA

安世

74HCT132D

Quad 2-input NAND Schmitt trigger

1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals

文件:269.66 Kbytes 页数:16 Pages

NEXPERIA

安世

74HCT132D

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

文件:70.63 Kbytes 页数:8 Pages

PHI

PHI

PHI

74HCT132DB

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

文件:70.63 Kbytes 页数:8 Pages

PHI

PHI

PHI

74HCT132N

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

文件:70.63 Kbytes 页数:8 Pages

PHI

PHI

PHI

74HCT132PW

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

文件:70.63 Kbytes 页数:8 Pages

PHI

PHI

PHI

74HCT132PW

Quad 2-input NAND Schmitt trigger

1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals

文件:269.66 Kbytes 页数:16 Pages

NEXPERIA

安世

74HCT132A

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs with LSTTL Compatible Inputs

文件:91.08 Kbytes 页数:8 Pages

ONSEMI

安森美半导体

74HCT132D-Q100

Quad 2-input NAND Schmitt trigger

文件:248.53 Kbytes 页数:19 Pages

NEXPERIA

安世

技术参数

  • VCC (V):

    4.5 - 5.5

  • Logic switching levels:

    TTL

  • Output drive capability (mA):

    ± 4

  • tpd (ns):

    17

  • fmax (MHz):

    36

  • Nr of bits:

    4

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    109

  • Ψth(j-top) (K/W):

    20.6

  • Rth(j-c) (K/W):

    67

  • Package name:

    SO14

供应商型号品牌批号封装库存备注价格
24+
5000
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ST
24+/25+
536
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ST
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PHI
23+
DIP-14
9856
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Harris
25+23+
SOP
25716
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23+
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50000
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Harris
25+
47
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TI
23+
3.9
3880
正品原装货价格低
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HARRIS
9840+
SOP
999
全新 发货1-2天
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恩XP
2016+
SOP
3000
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询价
更多74HCT132供应商 更新时间2026-3-17 16:00:00