High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA Asynchronous Set-Reset Capability ±4mA Output Drive at 5V Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs

文件：705.77 Kbytes 页数：6 Pages

SS

4-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word

文件：163.83 Kbytes 页数：28 Pages

PHI

飞利浦

4-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word

文件：163.83 Kbytes 页数：28 Pages

PHI

飞利浦

4-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word

文件：163.83 Kbytes 页数：28 Pages

PHI

飞利浦

5-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications.

文件：131.73 Kbytes 页数：28 Pages

PHI

飞利浦

5-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications.

文件：131.73 Kbytes 页数：28 Pages

PHI

飞利浦

5-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications.

文件：131.73 Kbytes 页数：28 Pages

PHI

飞利浦

Dual D-Type Flip Flop Preset and Clear

Features • High speed: fmax = 77 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28 VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays:

文件：277.71 Kbytes 页数：11 Pages

TOSHIBA

东芝

Dual D-type flip-flop with set and reset; positive edge-trigger

General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HI

文件：175.47 Kbytes 页数：21 Pages

恩XP

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

文件：299.12 Kbytes 页数：19 Pages

NEXPERIA

安世