8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

General description The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100

文件：219.95 Kbytes 页数：23 Pages

恩XP

8?묪it Serial?묲nput/Serial or Parallel.Output Shift Register with Latched 3?뭆tate Outputs

The 74HC595 consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8−bit latch. The shift register and latch have independent clock i

文件：160.83 Kbytes 页数：13 Pages

ONSEMI

安森美半导体

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

General description The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100

文件：219.95 Kbytes 页数：23 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

1. General description The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable c

文件：300.42 Kbytes 页数：20 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

8?묪it Serial?묲nput/Serial or Parallel?뭀utput Shift Register with Latched 3?뭆tate Outputs

The 74HC595 consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8−bit latch. The shift register and latch have independent clock i

文件：160.83 Kbytes 页数：13 Pages

ONSEMI

安森美半导体

8?묪it Serial?묲nput/Serial or Parallel?뭀utput Shift Register with Latched 3?뭆tate Outputs

The 74HC595 consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8−bit latch. The shift register and latch have independent clock i

文件：160.83 Kbytes 页数：13 Pages

ONSEMI

安森美半导体

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：287.98 Kbytes 页数：23 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司