8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift regi

文件：140.7 Kbytes 页数：28 Pages

PHI

飞利浦

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

General description The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. Features and benefits ■ 8-bit serial input ■ 8-bit serial or parallel output ■ Storage registe

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

1. General description The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading a

文件：327.56 Kbytes 页数：21 Pages

NEXPERIA

安世

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

General description The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100

文件：219.95 Kbytes 页数：23 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

1. General description The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable c

文件：300.42 Kbytes 页数：20 Pages

NEXPERIA

安世

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：374.02 Kbytes 页数：24 Pages

恩XP

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

文件：287.98 Kbytes 页数：23 Pages

NEXPERIA

安世

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR • 8-bit serial input\n• 8-bit serial or parallel output\n• Storage register with 3-state outputs\n• Shift register with direct clear\n• 100 MHz (typical) shift out frequency\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC595: CMOS level\n• For 74HCT595: TTL level\n\n• ESD protectio;

Nexperia

安世