4-to-16 line decoder/demultiplexer with input latches

The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the • Input levels:• For 74HC4514: CMOS level\n• For 74HCT4514: TTL level\n\n• 16-line demultiplexing capability\n• Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs\n• Complies with JEDEC standard no. 7 A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200;

Nexperia

安世

Package：24-SSOP（0.209"，5.30mm 宽）；包装：托盘 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC DECODER/DEMUX 1X4:16 24SSOP

Nexperia USA Inc.

Package：24-SSOP（0.209"，5.30mm 宽）；包装：托盘 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC DECODER/DEMUX 1X4:16 24SSOP

Nexperia USA Inc.

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

文件：76.3 Kbytes 页数：9 Pages

PHI

飞利浦

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

文件：276.68 Kbytes 页数：16 Pages

NEXPERIA

安世

High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches

文件：375.25 Kbytes 页数：16 Pages

TI

德州仪器