74HC4094DB

8-stage shift-and-store bus register

Generaldescription The74HC4094;74HCT4094isan8-bitserial-in/serialorparallel-outshiftregisterwithastorageregisterand3-stateoutputs.Boththeshiftandstorageregisterhaveseparateclocks.Thedevicefeaturesaserialinput(D)andtwoserialoutputs(QS1andQS2)toenablecasc

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74HC4094DB

8-stage shift-and-store bus register; • Complies with JEDEC standard JESD7A\n• Input levels:• For 74HC4094: CMOS level\n• For 74HCT4094: TTL level\n\n• Low-power dissipation\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃\n;

The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC4094DB-Q100

74HC4094DB-Q100 - 8-stage shift-and-store bus register; ·Automotive product qualification in accordance with AEC-Q100 (Grade 1)·Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

8-stage shift-and-store bus register - The 74HC4094-Q100; 74HCT4094-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74HC4094DB-Q100

8-stage shift-and-store bus register

74HC4094DB,112

Package：16-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 功能：串行至并行，串行 类别：集成电路（IC） 移位寄存器 描述：IC 8STAGE SHIFT/STORE BUS 16SSOP

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74HC4094DB,118

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：串行至并行，串行 类别：集成电路（IC） 移位寄存器 描述：IC 8STAGE SHIFT/STORE BUS 16SSOP

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74HC4094DB-Q100J

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：串行至并行，串行 类别：集成电路（IC） 移位寄存器 描述：IC SHIFT/STORE BUS 8STAGE 16SSOP

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