Triple 2-channel analog multiplexer/demultiplexer

General description The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.

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PHI

飞利浦

Triple 2-channel analog multiplexer/demultiplexer

General description The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each mul

文件：224.63 Kbytes 页数：32 Pages

恩XP

Triple 2-channel analog multiplexer/demultiplexer

文件：226.58 Kbytes 页数：32 Pages

恩XP

Triple 2-channel analog multiplexer/demultiplexer

文件：226.58 Kbytes 页数：32 Pages

恩XP

Triple 2-channel analog multiplexer/demultiplexer

The 74HC4053; 74HCT4053 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digi • Wide analog input voltage range from -5 V to +5 V\n• Complies with JEDEC standard no. 7A\n• Low ON resistance:• 80 Ω (typical) at VCC - VEE = 4.5 V\n• 70 Ω (typical) at VCC - VEE = 6.0 V\n• 60 Ω (typical) at VCC - VEE = 9.0 V\n\n• Logic level translation: to enable 5 V logic to communicate with ±5;

Nexperia

安世