Triple 2-channel analog multiplexer/demultiplexer

General description The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each mul

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Triple 2-channel analog multiplexer/demultiplexer

1. General description The 74HC4053; 74HCT4053 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a comm

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Triple 2-channel analog multiplexer/demultiplexer

1. General description The 74HC4053-Q100; 74HCT4053-Q100 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1)

文件：366.16 Kbytes 页数：25 Pages

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Triple 2-channel analog multiplexer/demultiplexer

General description The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Gr

文件：320.63 Kbytes 页数：30 Pages

恩XP

Triple 2-channel analog multiplexer/demultiplexer

1. General description The 74HC4053-Q100; 74HCT4053-Q100 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1)

文件：366.16 Kbytes 页数：25 Pages

NEXPERIA

安世

Triple 2-channel analog multiplexer/demultiplexer

General description The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Gr

文件：320.63 Kbytes 页数：30 Pages

恩XP

Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b

文件：147.89 Kbytes 页数：20 Pages

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Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b

文件：147.89 Kbytes 页数：20 Pages

PHI

PHI

Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b

文件：147.89 Kbytes 页数：20 Pages

PHI

PHI

Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b

文件：147.89 Kbytes 页数：20 Pages

PHI

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