74HC4053PW-Q100中文资料恩XP数据手册PDF规格书

General description

The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.

Features and benefits

■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)

◆ Specified from -40 °C to +85 °C and from -40 °C to +125 °C

■ Wide analog input voltage range from -5 V to +5 V

■ Low ON resistance:

◆ 80 Ω (typical) at VCC - VEE = 4.5 V

◆ 70 Ω (typical) at VCC - VEE = 6.0 V

◆ 60 Ω (typical) at VCC - VEE = 9.0 V

■ Logic level translation: to enable 5 V logic to communicate with 5 V analog signals

■ Typical ‘break before make’ built-in

■ ESD protection:

◆ MIL-STD-883, method 3015 exceeds 2000 V

◆ HBM JESD22-A114F exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

◆ CDM AEC-Q100-011 revision B exceeds 1000 V

■ Multiple package options

Applications

■ Analog multiplexing and demultiplexing

■ Digital multiplexing and demultiplexing

■ Signal gating