Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

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Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

文件：467.51 Kbytes 页数：34 Pages

PHI

飞利浦

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

文件：467.51 Kbytes 页数：34 Pages

PHI

飞利浦

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

文件：467.51 Kbytes 页数：34 Pages

PHI

飞利浦

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

文件：671.36 Kbytes 页数：36 Pages

NEXPERIA

安世

Phase-locked loop with VCO

1. General description The 74HC4046A-Q100 is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2.

文件：598.75 Kbytes 页数：32 Pages

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Phase-locked loop with VCO

1. General description The 74HC4046A-Q100 is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2.

文件：598.75 Kbytes 页数：32 Pages

NEXPERIA

安世

Phase-locked loop with VCO

The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. • Low power consumption\n• VCO-Inhibit control for ON/OFF keying and for low standby power consumption\n• Centre frequency of up to 17 MHz (typical) at VCC = 4.5 V\n• Choice of three phase comparators:• PC1: EXCLUSIVE-OR\n• PC2: Edge-triggered JK flip-flop\n• PC3: Edge-triggered RS flip-flop\n\n• Ex;

Nexperia

安世

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PHASE LOCK LOOP W/VCO 16SOIC

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL W/VCO 16-SSOP

Nexperia USA Inc.