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74HC40103

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:136.67 Kbytes 页数:17 Pages

PHI

飞利浦

PHI

74HC40103

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:144.11 Kbytes 页数:25 Pages

PHI

飞利浦

PHI

74HC40103

8-bit synchronous binary down counter

1. General description The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is de

文件:836.05 Kbytes 页数:23 Pages

NEXPERIA

安世

74HC40103

8-bit synchronous binary down counter

GENERAL DESCRIPTION\nThe 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.\nThe 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which is ac • Cascadable\n• Synchronous or asynchronous preset\n• Output capability: standard\n• ICC category: MSI ;

Renesas

瑞萨

74HC40103D

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:136.67 Kbytes 页数:17 Pages

ICST

74HC40103D

8-bit synchronous binary down counter

1. General description The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is de

文件:836.05 Kbytes 页数:23 Pages

NEXPERIA

安世

74HC40103D

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:144.11 Kbytes 页数:25 Pages

PHI

飞利浦

PHI

74HC40103D

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:136.67 Kbytes 页数:17 Pages

PHI

飞利浦

PHI

74HC40103DB

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:136.67 Kbytes 页数:17 Pages

PHI

飞利浦

PHI

74HC40103DB

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

文件:144.11 Kbytes 页数:25 Pages

PHI

飞利浦

PHI

技术参数

  • VCC (V):

    2.0 - 6.0

  • Output drive capability (mA):

    ± 5.2

  • Logic switching levels:

    CMOS

  • tpd (ns):

    15

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    56

  • Ψth(j-top) (K/W):

    1.0

  • Rth(j-c) (K/W):

    12

  • Package name:

    SO16

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更多74HC40103供应商 更新时间2025-12-5 9:31:00