Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

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Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO

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Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

文件：60.66 Kbytes 页数：7 Pages

PHI

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Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements

文件：255.75 Kbytes 页数：15 Pages

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Octal D-type flip-flop with data enable; positive-edge trigger

文件：721.41 Kbytes 页数：18 Pages

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Octal D-type flip-flop with data enable; positive-edge trigger

文件：721.41 Kbytes 页数：18 Pages

NEXPERIA

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Octal D-type flip-flop with data enable; positive-edge trigger

The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transit • Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC377: CMOS level\n• For 74HCT377: TTL level\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package;

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Octal D-type flip-flop with data enable; positive-edge trigger

The 74HC377‑Q100; 74HCT377‑Q100 is an octal positive‑edge triggered D‑type flip‑flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (C • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC377-Q100: CMOS level\n• For 74HCT377-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C;

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Octal D-type flip-flop with data enable; positive-edge trigger

The 74HC377‑Q100; 74HCT377‑Q100 is an octal positive‑edge triggered D‑type flip‑flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (C • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC377-Q100: CMOS level\n• For 74HCT377-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C;

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Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SO

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