Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT193 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous

文件：95.74 Kbytes 页数：13 Pages

PHI

PHI

Presettable synchronous 4-bit binary up/down counter

General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is hel

文件：157.98 Kbytes 页数：29 Pages

恩XP

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD i

文件：330.79 Kbytes 页数：24 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary up/down counter

文件：184.88 Kbytes 页数：30 Pages

恩XP

Presettable synchronous 4-bit binary up/down counter

General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is hel

文件：157.98 Kbytes 页数：29 Pages

恩XP

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed

文件：330.24 Kbytes 页数：24 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary up/down counter

文件：184.88 Kbytes 页数：30 Pages

恩XP

Presettable synchronous 4-bit binary up/down counter

文件：776.98 Kbytes 页数：29 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary up/down counter

文件：776.98 Kbytes 页数：29 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary up/down counter

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will • Input levels:• For 74HC193: CMOS level\n• For 74HCT193: TTL level\n\n• Synchronous reversible 4-bit binary counting\n• Asynchronous parallel load\n• Asynchronous reset\n• Expandable without external logic\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n•;

Nexperia

安世